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| 1 of 17 011806 sda 1 14 vcc scl 2 13 h0 a0 3 12 nc a1 4 11 h1 a2 5 10 l1 wp 6 9 nc gnd 7 8 l0 14-pin tssop (173-mil) a b c d 1 2 3 4 top view features two linear taper, temperature-controlled variable resistors ds1848-050 one 50k , 256 position one 10k , 256 position ds1848-010 two 10k , 256 position resistor settings changeable every 2c access to temperature data and device control via a 2-wire interface operates from 3v or 5v supplies packaging: 14-pin tssop, 16-ball csbga operating temperature: -40oc to +95oc programming temperature: 0oc to +70oc 128 bytes of user eeprom pin assignment description the ds1848 dual temperature-contro lled nonvolatile (nv) variable resistor consists of two 256- position linear, variable resistors. the ds1848-050 consists of one 10k and one 50k while the ds1848-010 consists of two 10k resistors; both incorporate a direct -to-digital temperature sensor. the device provides an ideal method for setting and temper ature-compensating bias voltages and currents in control applications using a minimum of circuitry. the variable resistors settings are stored in eeprom memory and can be accessed over the industry standard 2-wire serial bus. the valu e of each variable resistor is determined by a temperature-addressed look-up table, which can assign a unique value to each resistor for every 2c increment over the -40c to +95c range. the output of the digital temperature sens or is also available as a 13-bit, 2?s complement value over the serial bus. the interface i/o pins consist of sda and scl. ds1848 dual temperature-controlled nv variable resistor & memor y www.maxim-ic.com 16-ball csbga (4mm x 4mm)
ds1848 2 of 17 pin descriptions name tssop bga description v cc 14 a3 power supply terminal. the ds1848 will support supply voltages ranging from +3.0v to +5.5v. gnd 7 d1 ground terminal. sda 1 b2 2-wire serial data interface. the serial data pin is for serial data transfer to and from the ds1848. the pin is open drain and may be wire-ored with other ope n drain or open collector interfaces. scl 2 a2 2-wire serial clock input. the serial clock input is used to clock data into the ds1848 on risi ng edges and clock data out on falling edges. wp 6 c1 write protect input. if open or set to logi c 1, all memory, control registers, and look-up tables are write protected. if set to a logic 0, the device is not write protected and can be written to. the wp pin is pulled high internally. a0 3 a1 address input. pins a0, a1, and a2 are used to specify the address of each ds1848 when used in a multi-dropped configuration. a1 4 b1 address input. a2 5 c2 address input. h0 13 a4 high terminal of resistor 0. for both resistors, it is not required that the high termin al be connected to a potential greater than the low terminal. voltage applied to the high terminal of each resistor cannot exceed v cc , or go below ground. h1 11 b3 high terminal of resistor 1. l0 8 d3 low terminal of resistor 0. for both resistors, it is not required that the low terminal be connected to a potential less than the high terminal. voltage applied to the low terminal of each resistor cannot exceed v cc , or go below ground. l1 10 c4 low terminal of resistor 1. nc 9 d4 no connect. nc 12 b4 no connect. nc c3 no connect. nc d2 no connect. ds1848 3 of 17 ds1848 block diagram figure 1 2-wire interface digital temperature sensor 256 position digitally- controlled 10k or 50k resistor 0 256 position digitally- controlled 10k resistor 1 sd a scl h0 l0 h1 l1 table select byte configuration byte temperature msb byte temperature lsb byte address pointer user memory internal address sel user memory resistor 0 setting resistor 1 setting user memory 72x8 bit eeprom resistor 0 look-up table (table 1) 72x8 bit eeprom resistor 1 look-up table (table 2) a0 a1 a2 vcc gnd wp 128x8 bit user eeprom (table 0) 0h 7fh e0h e1h e2h e3h e4h e5h- e6h e7h e8h- efh f0h f1h f2h- ffh 0h 47h ds1848 4 of 17 memory location name of location function of location 00h to 47h (the table select byte, e0h, must be set to 01h or 02h to access the look- up tables) 00h to 7fh (the table select byte, e0h, must be set to 00h to access the user eeprom memory) user defined look-up table (lut) user memory this block contains the user-defined temperature settings of the resistors. values between 00h and ffh can be written to eith er table to set the 256 position variable resistors. the first address location, 00h, is used to set the resistor at -40c. each successive memory location will contain the resistor setting for the previous temperature +2c. for example, memory address 01h is the address that will set the resistor in a -38c environment. for default memory settings and programming the look-up table, refer to the programming the look-up table (lut) section of the datasheet. this block is for general-purpose user memory. when shipped from the factory, memory locations 60h ? 6bh contain the same information as found in look-up table 1, memory locations 28h ? 33h. memory locations 6ch ? 77h contain the same information as found in look-up table 2, memory locations 28h ? 33h. e0h table select byte writing to this byte determines if one of the two 72x8 eeprom look-up tables or the user eeprom memory is selected for reading or writing. 00h (user eeprom selected) 01h (look-up table 1 selected) 02h (look-up table 2 selected) e1h configuration byte tau ? temperature/address update ten ? temperature update enable aen ? address update enable default setting is 03h, tau = 1, ten = 1 and aen = 1. tau becomes a 1 after a temperature and address update has occurred as a result of a temperature conversion. the user can write this bit to 0 and check for a transition from 0 to 1 in order to verify that a conversion has occurred. if ten = 0, the temperature conversion feature is disabled. the user sets the resistor in ?manual mode? by writing to addresses f0h and f1h to control resistors 0 and 1, respectively. tau ten aen ds1848 5 of 17 memory location name of location function of location with aen = 0 the user can operate in a test mode. address updates made from the temperature sensor will cease. the user can load a memory location into e4h and verify that the values in locations f0h and f1h are the expected user-defined values. e2h temperature msb this byte contains the msb of the 13-bit 2s complement temperature output from the temperature sensor. e3h temperature lsb this byte contains the lsb of the 13-bit 2s complement temperature output from the temperature sensor. for example temperature readings, refer to table 2. e4h address pointer calculated, cu rrent resistor address (0h ? 47h). the user-defined resistor setting at this location in the respective look-up table will be loaded into f0h and f1h to set the two resistors. e5h to e6h user memory genera l purpose user memory (sram) e7h address select internal or exte rnal device address select. this byte allows the user to use the external address pins or an internal regi ster location to determine the device address. enb = 0 and external a2, a1, a0 grounded, device will use internal address bits (a2, a1, a0) in this register enb = 1, external a2, a1, a0 = any setting, device will use external address pins default setting is 01h. the device uses external pins to determine its address. e8h to efh user memory genera l purpose user memory (sram) f0h resistor 0 setting in the user-controlled setting mode, this block contains the resistor 0 setting. f1h resistor 1 setting in the user-controlled setting mode, this block contains the resistor 1 setting. f2h to ffh user memory genera l purpose user memory (sram) s 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 x x x a2 a1 a0 enb ds1848 6 of 17 programming the look -up table (lut) the following equation can be used to determine which resistor position setting, 00h ? ffh, should be written in the lut to achieve a given resistance at a specific temperature. 2 2 25 25 1 25 25 1 ) , , ( c z c y x c w c v u r c r pos ds1848-050 = 3.78964 for the 50k resistor = 19.74866 for the 10k resistor ds1848-010 = 8.394533 for both 10k resistors r = resistance desired at the output terminal c = temperature in degrees celsius u, v, w, x, y, and z are calibration constants progr ammed into each of the corresponding look-up tables. their addresses and lsb values are given in table 1 below. resistor 1 variables are found in look-up table 1 of the eeprom, and resist or 2 variables are found in look-up table 2. after these values are read, they should be overwritten with the appropriate temperature specif ic resistance settings. copies of these values can also be found in the user eeprom memory. look-up variable addresses table1 address in lut (hex) variable lsb 28 ? 29 u 2 -8 2a ? 2b v 10 -6 2c ? 2d w 10 -9 2e ? 2f x 2 -8 30 ? 31 y 10 -7 32 ? 33 z 10 -10 when shipped from the factory, all other memory loca tions in the luts are programmed to ffh (except bytes 00h-07h of table 1 and 2 which may be fact ory programmed to values other than ffh). note: memory locations 44h ? 47h, which cover the temper ature range (+96oc to +102oc), are outside of the specified operating temperature range (-40oc to +95oc). however, the values stored in these locations will act as valid resistance settings if the temperature exceeds +95oc. therefore, dallas semiconductor recommends that the user program a resist ance value into all lut locations. failure to do so will result in the part being set to the default value. ds1848 7 of 17 temperature conversion the direct-to-digital temperature sensor measures temperature through the use of an on-chip temperature measurement technique with an operating range fro m -40c to +95c. temp erature conversions are initiated upon power-up, and the most recent result is stored in a ddress locations e2h and e3h, which are updated every 10ms. temperature conversion will not occur during an active read or write to memory. the value of each resistor is determined by the te mperature-addressed look-up table that assigns a unique value to each resistor for every 2c increment with a 1c hysteresis at a temperature transition over the operating temperature range. this can be seen in figure 2. temperature conversion hysteresis figure 2 example temperature readings table 2 temp binary data hex data +95oc 0010 1111 1000 0000 2f80h +25.0625oc 0000 1100 1000 1000 0c88h -10.125oc 1111 1010 1111 0000 faf0h -40oc 1110 1100 0000 0000 ec00h 2 4 6 8 10 12 temperature (c) m6 m5 m4 m3 m2 m1 memory location increasing temp decreasing temp ds1848 8 of 17 2-wire operation clock and data transitions: the sda pin is normally pulled high with an external resistor or device. data on the sda pin may only change during scl low time periods. data changes during scl high periods will indicate a start or stop conditions depending on the conditions discussed below. refer to the timing diagram (figure 4) for further details. start condition: a high-to-low transition of sda with scl high is a start condition that must precede any other command. refer to the timing diagram (figure 4) for further details. stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command places the ds1848 into a low-power mode. refer to the timing diagram (figure 4) for further details. acknowledge: all address and data byte ar e transmitted via a serial prot ocol. the ds1848 pulls the sda line low during the ninth clock pulse to ac knowledge that it has received each word. standby mode: the ds1848 features a low-power mode that is automatically enabled after power-on, after a stop command, and after the comp letion of all inte rnal operations. 2-wire interface reset: after any interruption in protocol, power loss, or system reset, the following steps reset the ds1848. 1. clock up to nine cycles. 2. look for sda high in each cycle while scl is high. 3. create a start condition while sda is high. device addressing: the ds1848 must receive an 8-bit device address word following a start condition to enable a specific device for a read or write operation. the address wo rd is clocked into the ds1848 msb to lsb. the address word consists of ah (10106) followed by a2, a1, and a0 then the r/w bit. if the r/w bit is high, a read operation is initiated. if the r/w is low, a write operation is initiated. for a device to become active, the values of a2, a1 and a0 must be the same as the hard-wired address pins on the ds1848. upon a match of written and hard-wired addresses, the ds1848 will output a zero for one clock cycle as an acknowledge. if th e address does not match, the ds1848 returns to a low- power mode. write operations: after receiving a matching address byte with the r/w bit set low, the device goes into the write mode of operation. the master must transmit an 8-b it eeprom memory address to the device to define the address where the data is to be written. after byte has been received, the ds1848 will transmit a zero for one clock cycle to acknowledge th e receipt of the address. the master must then transmit an 8-bit data word to be written into this address. the ds 1848 will again transmit a zero for one clock cycle to acknowledge the receipt of the data. at this point, the master must terminate the write operation with a stop condition. the ds1848 then enters an internally timed write process t w to the eeprom memory. all inputs are disabled during this byte write cycle. the ds1848 is capable of an 8-byte page write. a page write is initiated the same way as a byte write, but the master does not send a stop condition after the first byte. instead, after the slave acknowledges receipt of the data byte, the master can send up to se ven more bytes using the same nine-clock sequence. ds1848 9 of 17 the master must terminate the write cycle with a stop condition or the data clocked into the ds1848 will not be latched into permanent memory. acknowledge polling: once the internally-timed write has star ted and the ds1848 inputs are disabled, acknowledge polling can be initiated. the process i nvolves transmitting a start condition followed by the device address. the r/w bit signifies the type of operation that is desired. th e read or write sequence will only be allowed to proceed if the internal wr ite cycle has completed and the ds1848 responds with a zero. read operations: after receiving a matching address byte with the r/w bit set high, the device goes into the read mode of operation. there are three r ead operations: current address read, random read, and sequential addr ess read. current address read the ds1848 has an internal address regi ster that maintains the address us ed during the last read or write operation, incremented by one. this da ta is maintained as long as v cc is valid. if the most recent address was the last byte in memory, then the register resets to the first address. this address stays valid between operations as long as power is available. once the device address is clocked in and acknowledge d by the ds1848 with the r/w bit set to high, the current address data word is clocked out. the master does not respond with a zero, but does generate a stop condition afterwards. random read a random read requires a dummy byte write sequence to load in the data word address. once the device and data address bytes are clocke d in by the master and acknowledged by the ds1848, the master must generate another start condition. th e master now initiates a current a ddress read by sending the device address with the read/write bit set high. the ds1848 will acknowledge the device address and serially clocks out the data byte. sequential address read sequential reads are initiated by either a current address read or a random address read. after the master receives the first data byte, the master responds w ith an acknowledge. as long as the ds1848 receives this acknowledge after a byte is read, the master may clock out additional data words from the ds1848. after reaching address ffh, it resets to address 00h. the sequential read operation is terminated when the master initiates a stop condition. the master does not respond with a zero. for a more detailed description of 2-wire theory of operation, refer to the next section. ds1848 10 of 17 2-wire serial port operation the 2-wire serial port interface supports a bi-dir ectional data transmission protocol with device addressing. a device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a ?master.? the devices that are controlled by the master are ?slaves.? the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates th e start and stop conditions. the ds1848 operates as a slave on the 2-wire bus. connecti ons to the bus are made via the open-drain i/o lines sda and scl. the following i/o terminals control the 2-wire serial port: sda, scl, a0, a1, a2. timing diagrams for the 2-wire serial port can be found in figures 3 and 4. timing information for the 2-wire serial port is provided in the ac electrical characteristic s table for 2-wire serial communications. the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid da ta when, after a start condition, the data line is stable for the duration of the high period of th e clock signal. the data on the line can be changed during the low period of the clock signal. there is one clock pulse per bit of data . figures 3 and 4 detail how data transfer is accomplishe d on the two-wire bus. depending upon the state of the r/w bit, two types of data transfer are possible. each data transfer is initiated with a start c ondition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferre d byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications a regular mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1848 works in both modes. acknowledge: each receiving device, when addressed, is ob liged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into acc ount. a master must signal an end of data to the ds1848 11 of 17 slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to en able the master to gene rate the stop condition. 1. data transfer from a master transmitter to a slave r eceiver. the first byte transmitted by the master is the command/control byte. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the command/control byte) to the slave. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? can be returned. the master device generates all se rial clock pulses and the start an d stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1848 may operate in the following two modes: 1. slave receiver mode: serial data and clock are received through sda and scl respectively. after each byte is received, an acknowledge bit is tran smitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave (device) address and direction bit. 2. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ds1848, while the seri al clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. 3. slave address: command/control byte is the firs t byte received following the start condition from the master device. the command/control byte consists of a 4-bit control code. for the ds1848, this is set as 1010 binary for read/write operations. the next 3 bits of the command/ control byte are the device select bits or slave address (a2, a1, a0). they are used by the master device to select which of eight devices is to be accessed. when readin g or writing the ds1848, the device-select bits must match the device-select pins (a2, a1, a0). the la st bit of the command/control byte (r/w) defines the operation to be performed. when set to a 1, a re ad operation is selected, and when set to a 0, a write operation is selected. following the start condition, the ds1848 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1010 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an acknowledge signal on the sda line. write protect the write-protect input pin (wp) protects all memory (including eeprom), control registers, and look- up tables from alteration in an application. however, this does not interfere with internal temperature/resistor updates. if set to a logic 0, the device is not write protected and can be written to via the 2-wire interface. this pin has an internal pull-up resistor. ds1848 12 of 17 2-wire data transfer protocol figure 3 2-wire ac characteristics figure 4 ds1848 13 of 17 absolute maximum ratings* voltage on any pin relative to ground -0.3v to +6.0v operating temperature -40c to +95c programming temperature 0c to +70c storage temperature -55c to +125c soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operation s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-40 c to +95 c) parameter symbol condition min typ max units notes supply voltage vcc +3.0 5.5 v 1 resistor inputs l0, l1, h0, h1 gnd-0.3 v cc +0.3 v resistor current i resistor ds1848-050 ds1848-010 -1 -3 1 3 ma dc electrical characteristics (-40c to +95c; v cc = 3.0v to 5.5v) parameter symbol condition min typ max units notes supply current i cc 0.5 1 ma 2 input leakage (digital inputs) i l -1 +1 a input leakage (h0, h1, l0, and l1) i l -100 +100 na input logic 1 v ih 0.7v cc v cc +0.3 v 15 input logic 0 v il gnd-0.3 0.3v cc v input current each i/o pin 0.4 ds1848 15 of 17 ac electrical characteristics (-40 c to +95 c, v cc = 3.0v to 5.5v) parameter symbol condition min typ max units notes scl clock frequency f scl fast mode standard mode 0 0 400 100 khz 6 bus free time between stop and start t buf fast mode standard mode 1.3 4.7 s 6 hold time (repeated) start condition t hd:sta fast mode standard mode 0.6 4.0 s 7,6 low period of scl clock t low fast mode standard mode 1.3 4.7 s 6 high period of scl clock t high fast mode standard mode 0.6 4.0 s 6 data hold time t hd:dat fast mode standard mode 0 0 0.9 s 6,8,9 data set-up time t su:dat fast mode standard mode 100 250 ns 6 start set-up time t su:sta fast mode standard mode 0.6 4.7 s 6 rise time of both sda and scl signals t r fast mode standard mode 20+0.1c b 300 1000 ns 10 fall time of both sda and scl signals t f fast mode standard mode 20+0.1c b 300 300 ns 10 set-up time for stop condition t su:sto fast mode standard mode 0.6 4.0 s capacitive load for each bus line c b 400 pf 10 eeprom write time t w 5 20 ms 11 nonvolatile memory characteristics parameter symbol condition min typ max units writes 85 c 50,000 ds1848 16 of 17 notes : 1) all voltages are referenced to ground. 2) inputs sda = scl = wp = vcc. a0, a1, and a2 must be tied to v cc or gnd. 3) valid at 25 c only. 4) absolute linearity is the difference of measur ed value from expected value at dac position. expected value is a straight line from measur ed minimum position to measured maximum position. 5) relative linearity the deviation of an lsb dac setting change vs. the expected lsb change. expected lsb change is the slope of the straight line from measured minimum position to measured maximum position. 6) a fast mode device can be used in a standard mode system, but the requirement t su:dat > 250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000ns + 250ns = 1250ns before the scl line is released. 7) after this period, the firs t clock pulse is generated. 8) the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 9) a device must internally provide a hold time of at least 300ns for th e sda signal (referred to the vi h min of the scl signal) in order to bridge the undefined region of the falling edge of scl. 10) c b ? total capacitance of one bus line in picofarads, timing referenced to 0.9v cc and 0.1v cc . 11) eeprom write begins after a stop condition occurs. 12) the temperature coefficient varies with resistor position from 650ppm/c at position ffh to 1000ppm/c at 00h (for the 50k resistor), or 1500ppm/c at 00h (for the 10k resistor). see the graphs below. the tempco can be significantly reduced by using the resistor calibration values. when doing so, the average tempco over the entire temper ature range is between 200ppm/c (for the lower positions) and 10ppm/c (higher positions). refer to the programming the look-up table section of the data sheet. 13) i/o pins of fast mode devices must not obstruct the sda and scl lines if v cc is switched off. 14) refer to programming the look-up table section of the data sheet for calibration. 15) address input a1 passes la tch-up per jedec 78 class i. all other pins pass class ii. ordering information ordering package operating version tempco vs. resistance 10k resistor 500 600 700 800 900 1000 1100 1200 1300 1400 1500 0 2000 4000 6000 8000 10000 resistance (ohms) ppm/c tempco vs. resistance 50k resistor 500 600 700 800 900 1000 1100 0 10000 20000 30000 40000 50000 resistance (ohms) ppm/c ds1848 17 of 17 number temperature resistor 0 /resistor 1 ds1848e-010 14-pin tssop (173- mil) -40oc to +95oc 10k /10k ds1848e-050 14-pin tssop (173- mil) -40oc to +95oc 50k /10k ds1848e-010/t&r 14-pin tssop/tape & reel -40oc to +95oc 10k /10k ds1848e-050/t&r 14-pin tssop/tape & reel -40oc to +95oc 50k /10k ds1848b-010 16-ball csbga -40oc to +95oc 10k /10k ds1848b-050 16-ball csbga -40oc to +95oc 50k /10k ds1848b-010+ 16-ball csbga lf -40oc to +95oc 10k /10k ds1848b-010+t&r 16-ball csbga lf t&r -40oc to +95oc 10k /10k ds1848b-010/t&r 16-ball csbga t&r -40oc to +95oc 10k /10k ds1848b-050+ 16-ball csbga lf -40oc to +95oc 50k /10k ds1848b-050+t&r 16-ball csbga lf t&r -40oc to +95oc 50k /10k ds1848b-050/t&r 16-ball csbga t&r -40oc to +95oc 50k /10k ds1848e-010+ 14-pin tssop ( 173-mil) -40oc to +95oc 10k /10k ds1848e-010+t&r 14-pin tssop lf t&r -40oc to +95oc 10k /10k ds1848e-050+ 14-pin tssop ( 173-mil) -40oc to +95oc 50k /10k ds1848e-050+t&r 14-pin tssop lf t&r -40oc to +95oc 50k /10k + denotes lead-free package. english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members ds1848 part number table notes: see the ds1848 quickview data sheet for further information on this product family or download the ds1848 full data sheet (pdf, 264kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number notes free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1848b-c50/t&r csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848b-c50 csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848b-c10/t&r csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848b-c10 csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848b-010 10kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848b-050+t&r 10k/50kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848b-050+ 10k/50kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848b-010+t&r 10kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848b-010+ 10kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848b-050 10k/50kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848b-010/t&r 10kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848b-050/t&r 10k/50kohms csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * -40c to +85c rohs/lead-free: no materials analysis ds1848/nre -40c to +85c rohs/lead-free: no ds1848e-010 10kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14-2 * -40c to +85c rohs/lead-free: no materials analysis ds1848e-050+t&r 10k/50kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848e-050+ 10k/50kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848e-010+t&r 10kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848e-010+ 10kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1848e-050 10k/50kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14-2 * -40c to +85c rohs/lead-free: no materials analysis ds1848e-010/t&r 10kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14-2 * -40c to +85c rohs/lead-free: no materials analysis ds1848e-050/t&r 10k/50kohms tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14-2 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? contact us: send us an email copyright 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy |
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